mlx5dv_alloc_dm - Man Page

allocates device memory (DM)

Synopsis

#include <infiniband/mlx5dv.h>

struct ibv_dm *mlx5dv_alloc_dm(struct ibv_context *context,
                   struct ibv_alloc_dm_attr *dm_attr,
                   struct mlx5dv_alloc_dm_attr *mlx5_dm_attr)

Description

mlx5dv_alloc_dm() allocates device memory (DM) with specific driver properties.

Arguments

Please see ibv_alloc_dm(3) man page for context and dm_attr.

mlx5_dm_attr

struct mlx5dv_alloc_dm_attr {
    enum mlx5dv_alloc_dm_type type;
    uint64_t comp_mask;
};
type

The device memory type user wishes to allocate:

MLX5DV_DM_TYPE_MEMIC Device memory of type MEMIC - On-Chip memory that can be allocated and used as memory region for transmitting/receiving packet directly from/to the memory on the chip.

MLX5DV_DM_TYPE_STEERING_SW_ICM Device memory of type STEERING SW ICM - This memory is used by the device to store the packet steering tables and rules. Can be used for direct table and steering rules creation when allocated by a privileged user.

MLX5DV_DM_TYPE_HEADER_MODIFY_SW_ICM Device memory of type HEADER MODIFY SW ICM - This memory is used by the device to store the packet header modification tables and rules. Can be used for direct table and header modification rules creation when allocated by a privileged user.

MLX5DV_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM Device memory of type HEADER MODIFY PATTERN SW ICM - This memory is used by the device to store packet header modification patterns/templates. Can be used for direct table and header modification rules creation when allocated by a privileged user.

MLX5DV_DM_TYPE_ENCAP_SW_ICM Device memory of type PACKET ENCAP SW ICM - This memory is used by the device to store packet encap data. Can be used for packet encap reformat rules creation when allocated by a privileged user.

comp_mask

Bitmask specifying what fields in the structure are valid: Currently reserved and should be set to 0.

Return Value

mlx5dv_alloc_dm() returns a pointer to the created DM, on error NULL will be returned and errno will be set.

See Also

ibv_alloc_dm(3),

Author

Ariel Levkovich lariel@mellanox.com\c

Referenced By

mlx5dv_dm_map_op_addr(3).

2018-9-1 mlx5 Programmer’s Manual