cpu_id_t - Man Page

cpu_architecture_t architecture
cpu_feature_level_t feature_level
char vendor_str [VENDOR_STR_MAX]
char brand_str [BRAND_STR_MAX]
cpu_vendor_t vendor
uint8_t flags [CPU_FLAGS_MAX]
int32_t family
int32_t model
int32_t stepping
int32_t ext_family
int32_t ext_model
union {
  struct x86_id_t x86
  struct arm_id_t arm
};
int32_t num_cores
int32_t num_logical_cpus
int32_t total_logical_cpus
int32_t l1_data_cache
int32_t l1_instruction_cache
int32_t l2_cache
int32_t l3_cache
int32_t l4_cache
int32_t l1_assoc
int32_t l1_data_assoc
int32_t l1_instruction_assoc
int32_t l2_assoc
int32_t l3_assoc
int32_t l4_assoc
int32_t l1_cacheline
int32_t l1_data_cacheline
int32_t l1_instruction_cacheline
int32_t l2_cacheline
int32_t l3_cacheline
int32_t l4_cacheline
int32_t l1_data_instances
int32_t l1_instruction_instances
int32_t l2_instances
int32_t l3_instances
int32_t l4_instances
char cpu_codename [CODENAME_STR_MAX]
int32_t sse_size
uint8_t detection_hints [CPU_HINTS_MAX]
struct cpu_sgx_t sgx
cpu_affinity_mask_t affinity_mask
cpu_purpose_t purpose
char technology_node [TECHNOLOGY_STR_MAX]

contains architecture specific info​. Use cpu_id_t::architecture to know which member is valid​.

bitmask of the affinity ids this processor type is occupying

contains the CPU architecture ID (e​.g​. ARCHITECTURE_X86)

contains the brand string, e​.g​. "Intel(R) Xeon(TM) CPU 2​.40GHz"

The brief and human-friendly CPU codename, which was recognized​.
Examples:

+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+
| Vendor | Family | Model | Step​. | Cache |       Brand String                    | cpu_id_t​.cpu_codename |
+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+
| AMD    |      6 |     8 |     0 |   256 | (not available - will be ignored)     | "K6-2"                |
| Intel  |     15 |     2 |     5 |   512 | "Intel(R) Xeon(TM) CPU 2​.40GHz"       | "Xeon (Prestonia)"    |
| Intel  |      6 |    15 |    11 |  4096 | "Intel(R) Core(TM)2 Duo CPU E6550​.​.​." | "Conroe (Core 2 Duo)" |
| AMD    |     15 |    35 |     2 |  1024 | "Dual Core AMD Opteron(tm) Proces​.​.​." | "Opteron (Dual Core)" |
+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+

contain miscellaneous detection information​. Used to test about specifics of certain detected features​. See CPU_HINT_* macros below​.

See also

Hints

CPU display ("true") family (computed as BaseFamily[3:0]+ExtendedFamily[7:0])

Deprecated

replaced by x86_id_t::ext_family (prefix member with x86​., e​.g​. id​.x86​.ext_family)

CPU display ("true") model (computed as (ExtendedModel[3:0]<<4) + BaseModel[3:0]) For detailed discussion about what BaseModel / ExtendedModel / Model are, see Github issue #150​.

Deprecated

replaced by x86_id_t::ext_model (prefix member with x86​., e​.g​. id​.x86​.ext_model)

CPU family (BaseFamily[3:0])

Deprecated

replaced by x86_id_t::family (prefix member with x86​., e​.g​. id​.x86​.family)

contains the CPU feature level, also know as microarchitecture levels (x86) and architecture version (ARM)

contain CPU flags​. Used to test for features​. See the CPU_FEATURE_* macros below​.

See also

Features

Cache associativity for the L1 data cache​. -1 if undetermined

Deprecated

replaced by cpu_id_t::l1_data_assoc

Cache-line size for L1 data cache​. -1 if undetermined

Deprecated

replaced by cpu_id_t::l1_data_cacheline

Cache associativity for the L1 data cache​. -1 if undetermined

L1 data cache size in KB​. Could be zero, if the CPU lacks cache​. If the size cannot be determined, it will be -1​.

Cache-line size for L1 data cache​. -1 if undetermined

Number of L1 data cache instances​. -1 if undetermined

Cache associativity for the L1 instruction cache​. -1 if undetermined

L1 instruction cache size in KB​. Could be zero, if the CPU lacks cache​. If the size cannot be determined, it will be -1​.

Note

On some Intel CPUs, whose instruction cache is in fact a trace cache, the size will be expressed in K uOps​.

Cache-line size for L1 instruction cache​. -1 if undetermined

Number of L1 instruction cache instances​. -1 if undetermined

Cache associativity for the L2 cache​. -1 if undetermined

L2 cache size in KB​. Could be zero, if the CPU lacks L2 cache​. If the size of the cache could not be determined, it will be -1

Cache-line size for L2 cache​. -1 if undetermined

Number of L2 cache instances​. -1 if undetermined

Cache associativity for the L3 cache​. -1 if undetermined

L3 cache size in KB​. Zero on most systems

Cache-line size for L3 cache​. -1 if undetermined

Number of L3 cache instances​. -1 if undetermined

Cache associativity for the L4 cache​. -1 if undetermined

L4 cache size in KB​. Zero on most systems

Cache-line size for L4 cache​. -1 if undetermined

Number of L4 cache instances​. -1 if undetermined

CPU model (BaseModel[3:0])

Deprecated

replaced by x86_id_t::model (prefix member with x86​., e​.g​. id​.x86​.model)

Number of CPU cores on the current processor

Number of logical processors on the current processor​. Could be more than the number of physical cores, e​.g​. when the processor has HyperThreading​.

processor type purpose, relevant in case of hybrid CPU (e​.g​. PURPOSE_PERFORMANCE)

contains information about SGX features if the processor, if present

Deprecated

replaced by x86_id_t::sgx (prefix member with x86​., e​.g​. id​.x86​.sgx)

SSE execution unit size (64 or 128; -1 if N/A)

Deprecated

replaced by x86_id_t::sse_size (prefix member with x86​., e​.g​. id​.x86​.sse_size)

CPU stepping

Deprecated

replaced by x86_id_t::stepping (prefix member with x86​., e​.g​. id​.x86​.stepping)

contains the technology node string, e​.g​. "32 nm"

The total number of logical processors​. The same value is available through cpuid_get_total_cpus​.

This is num_logical_cpus * {total physical processors in the system} (but only on a real system, under a VM this number may be lower)​.

If you're writing a multithreaded program and you want to run it on all CPUs, this is the number of threads you need​.

Note

in a VM, this will exactly match the number of CPUs set in the VM's configuration​.

contains the recognized CPU vendor

contains the CPU vendor string, e​.g​. "GenuineIntel"