qucsveri - Man Page

qucsveri [OPTION] infile outfile time dir bindir

Qucs is an integrated circuit simulator which means you are able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can view the simulation results on a presentation page or window.

The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, harmonic balance analysis, noise analysis, etc.

QucsVeri is a wrapper script for digital simulations performed by Qucs.  The program utilizes the Icarus Verilog compiler in order to convert the Verilog output of Qucs into a iverilog program.  This file is then executed using vvp and its VCD output file is converted to a Qucs dataset.

INFILE

the filename of the Verilog file to be simulated located in the directory specified in DIR

OUTFILE

the filename of the Qucs dataset file to be produced

TIME

duration of the digital simulation

DIR

the name of the directory where the simulation is going to be performed

BINDIR

the location where the qucsconv program is installed

The latest version of Qucs can always be obtained from https://sf.net/p/qucs

Known bugs are documented within the BUGS file.  Report bugs to qucs-bugs@lists.sourceforge.net

Copyright © 2007 Stefan Jahn <stefan@lkcc.org>

This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Written by Michael Margraf <michael.margraf@alumni.tu-berlin.de> and Stefan Jahn <stefan@lkcc.org>.